Wen Ben Jone

Wen Ben Jone

Associate Professor

Rhodes Hall

834

CEAS - Elec Eng & Computer Science - 0030

Professional Summary

Wen-Ben Jone was an Assistant and Associate Professor of the Department of Computer Science at New Mexico Institute of Mining and Technology, Socorro, New Mexico, 1987-1993. From 1993 to 2000, he joined the Department of Computer Engineering and Information Science, National Chung-Cheng University, Chiayi, Taiwan, as a Visiting Associate Professor and then a Full professor. From 2001, he has been an Associate Professor of the Department of Electrical Engineering & Computing Systems, University of Cincinnati. He has advised more than 70 MS/PhD theses in the area of VLSI design and test. He has published more than 60 journal papers and 100 conference papers. Dr. Jone is a co-recipient of the 2003 IEEE Donald G. Fink Prize Paper Award, the best paper award of 2008 International Symposium on Low-Power Electronics & Design, and 2012 International Symposium on VLSI Design, Automation & Test.  He has been a program committee of VLSI-related conferences such as IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Education

PhD: Case Western Reserve University Cleveland, Ohio, 1987 (computer engineering)

MS: National Chao-Tung University Hsin-Chu, Taiwan, 1981 (computer engineering)

BS: National Chao-Tung University Hsin-Chu, Taiwan, 1979 (Computer Science)

Research and Practice Interests

Reliable VLSI system design, low-power VLSI system design, many-core micro-processor design & parallel computing, VLSI system testing & design for testability, VLSI design for deep learning.

Research Support

Grant: #CCF-0541103 Investigators:Hu, Yiming; Jone, Wen Ben 05-01-2006 -04-30-2010 National Science Foundation Selective Way Activation of Set-Associativity Cache Role:Collaborator $390,000.00 Closed Level:Federal

Publications

Peer Reviewed Publications

Han Q.;Xu Q.;Jone W. (01-01-2018. ) SERA: statistical error rate analysis for profit-oriented performance binning of resilient circuits.Integration, the VLSI Journal, , 60 ,1-12 More Information

Peng Y.;Chen C.;Tsai H.;Yang K.;Huang P.;Chang S.;Jone W.;Chen T. (03-01-2017. ) Leak stopper: An actively revitalized snoop filter architecture with effective generation control.ACM Transactions on Design Automation of Electronic Systems, , 22 (3 ) , More Information

Chou H.;Chen Y.;Yang K.;Tsao J.;Chang S.;Jone W.;Chen T. (03-01-2016. ) High-performance deadlock-free ID assignment for advanced interconnect protocols.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 24 (3 ) ,1169-1173 More Information

Chou H.;Hsiao M.;Chen Y.;Yang K.;Tsao J.;Lung C.;Chang S.;Jone W.;Chen T. (09-01-2015. ) Soft-error-tolerant design methodology for balancing performance, power, and reliability.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 23 (9 ) ,1628-1639 More Information

Han Q.;Guo J.;Xu Q.;Jone W. (03-29-2015. ) On resilient system performance binning.Proceedings of the International Symposium on Physical Design, , 29-March-2015 ,119-125 More Information

Lam T.;Wei X.;Jone W.;Diao Y.;Wu Y. (01-01-2014. ) On macro-fault: A new fault model, its implications on fault tolerance and manufacturing yield.Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, , 233-234 More Information

Han Q.;Guo J.;Jone W.;Xu Q. (12-01-2013. ) Path delay testing in resilient system.Midwest Symposium on Circuits and Systems, , 645-648 More Information

Guo J.;Han Q.;Jone W.;Wu Y. (12-01-2013. ) A cross-layer fault-tolerant design method for high manufacturing yield and system reliability.Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, , 71-76 More Information

Chen S.;Hsiao M.;Jone W.;Chen T. (08-15-2013. ) A configurable bus-tracer for error reproduction in post-silicon validation.2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, , More Information

Yuan F.;Liu Y.;Jone W.;Xu Q. (07-12-2013. ) On testing timing-speculative circuits.Proceedings - Design Automation Conference, , More Information

Ye R.;Yuan F.;Sun Z.;Jone W.;Xu Q. (07-12-2013. ) Post-placement voltage island generation for timing-speculative circuits.Proceedings - Design Automation Conference, , More Information

Kim H.;Wang L.;Wu Y.;Jone W. (02-14-2013. ) Testing of synchronizers in asynchronous FIFO.Journal of Electronic Testing: Theory and Applications (JETTA), , 29 (1 ) ,49-72 More Information

Chen S.Y.;Wen C.N.;Yang G.H.;Jone W.B.;Chen T.F. (07-25-2012. ) IMITATOR: A deterministic multicore replay system with refining techniques.2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers, , More Information

Wu S.;Wang L.;Wen X.;Jone W.;Hsiao M.;Li F.;Li J.;Huang J. (01-01-2012. ) Launch-on-shift test generation for testing scan designs containing synchronous and asynchronous clo.ACM Transactions on Design Automation of Electronic Systems, , 17 (4 ) , More Information

Xu H.;Jone W.B.;Vemuri R. (07-01-2011. ) Aggressive runtime leakage control through adaptive light-weight V th hopping.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 19 (7 ) ,1319-1323 More Information

Wu S.;Wang L.;Wen X.;Jiang Z.;Tan L.;Zhang Y.;Hu Y.;Jone W.;Hsiao M.;Li J.;Huang J.;Yu L. (03-01-2011. ) Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domai.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 30 (3 ) ,455-463 More Information

Xu H.;Vemuri R.;Jone W. (02-01-2011. ) Dynamic characteristics of power gating during mode transition.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 19 (2 ) ,237-249 More Information

Nemeth J.;Min R.;Jone W.B.;Hu Y. (01-01-2011. ) Location cache design and performance analysis for chip multiprocessors.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 19 (1 ) ,104-117 More Information

Xiong X.;Wu Y.;Jone W. (12-01-2010. ) Control circuitry for self-repairable MEMS accelerometers.Technological Developments in Education and Automation, , 265-270 More Information

Xu H.;Vemuri R.;Jone W. (12-01-2010. ) Current shaping and multi-thread activation for fast and reliable power mode transition in multicore.IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, , 637-641 More Information

Xu H.;Jone W.;Vemuri R. (12-01-2010. ) Stretching the limit of microarchitectural level leakage control with adaptive light-weight Vth hopp.IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, , 632-636 More Information

Wu S.;Wang L.;Yu L.;Furukawa H.;Wen X.;Jone W.;Touba N.;Zhao F.;Liu J.;Chao H.;Li F.;Jiang Z. (12-01-2010. ) Logic BIST architecture using staggered launch-on-shift for testing designs containing asynchronous .Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, , 358-366 More Information

Xu H.;Jone W.B.;Vemuri R. (10-01-2010. ) Tuning Vth hopping for aggressive runtime leakage control.Journal of Low Power Electronics, , 6 (3 ) ,447-456 More Information

Ramakrishnan D.;Wu Y.;Jone W. (08-01-2010. ) Design and analysis of location caches in a NoC-based chip multiprocessor system.Journal of Low Power Electronics, , 6 (2 ) ,240-262 More Information

Kim H.;Jone W.;Wang L. (06-01-2010. ) Fault modeling and analysis for resistive bridging defects in a synchronizer.Journal of Electronic Testing: Theory and Applications (JETTA), , 26 (3 ) ,367-392 More Information

Xu H.;Jone W.;Vemuri R. (03-31-2010. ) Novel Vth hopping techniques for aggressive runtime leakage control.Proceedings of the IEEE International Conference on VLSI Design, , 51-56 More Information

Wang L.;Wen X.;Wu S.;Furukawa H.;Chao H.;Sheu B.;Guo J.;Jone W. (02-01-2010. ) Using launch-on-capture for testing BIST designs containing synchronous and asynchronous clock domai.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 29 (2 ) ,299-312 More Information

Kim H.;Jone W.;Wang L. (12-01-2009. ) Analysis of resistive open defects in a synchronizer.Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, , 164-172 More Information

Xu H.;Vemuri R.;Jone W.B. (12-01-2009. ) Temporal and spatial idleness exploitation for optimal-grained leakage control .IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, , 468-473

Kim H.;Jone W.;Wang L.;Wu S. (12-01-2009. ) Analysis of resistive bridging defects in a synchronizer.Proceedings of the Asian Test Symposium, , 443-449 More Information

Das S.;Hossain A.;Li J.;Petriu E.;Biswas S.;Jone W.;Assaf M. (11-25-2009. ) Further studies on improved test efficiency in cores-based system-on-chips using ModelSim verificati.2009 IEEE Intrumentation and Measurement Technology Conference, I2MTC 2009, , 1138-1143 More Information

Hao X.;Vemuri R.;Jone W. (10-22-2009. ) Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic .Proceedings -Design, Automation and Test in Europe, DATE, , 594-597

Xu H.;Jone W.;Vemuri R. (12-26-2008. ) Accurate energy Breakeven time estimation for run-time power gating.IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, , 161-168 More Information

Xu H.;Vemuri R.;Jone W. (12-17-2008. ) Dynamic virtual ground voltage estimation for power gating.Proceedings of the International Symposium on Low Power Electronics and Design, , 27-32 More Information

Kim H.;Jone W. (12-01-2008. ) Fault modeling and analysis for bridging defects in a synchronizer.National Aerospace and Electronics Conference, Proceedings of the IEEE, , 397-403 More Information

Liu C.;Chakrabarty K.;Jone W. (12-01-2008. ) System/Network-On-Chip Test Architectures.System-on-Chip Test Architectures, , 171-224 More Information

Xiong X.;Wu Y.;Jone W. (12-01-2008. ) Reliability model for MEMS accelerometers.Novel Algorithms and Techniques in Telecommunications, Automation and Industrial Electronics, , 261-266 More Information

Xiong X.;Wu Y.;Jone W. (12-01-2008. ) Material fatigue and reliability of MEMS accelerometers.Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, , 314-322 More Information

Xu H.;Vemuri R.;Jone W. (12-01-2008. ) Run-time active leakage reduction by power gating and reverse body biasing: An energy view.26th IEEE International Conference on Computer Design 2008, ICCD, , 618-625 More Information

Wang L.;Apte R.;Wu S.;Sheu B.;Lee K.;Wen X.;Jone W.;Yeh C.;Wang W.;Chao H.;Guo J.;Liu J.;Niu Y.;Sung Y.;Wang C.;Li F. (12-01-2008. ) Turbo1500: Toward core-based design for test and diagnosis using the IEEE 1500 standard.Proceedings - International Test Conference, , More Information

Pan X.;Jone W.;Das S. (09-15-2008. ) Performance analysis for clock and data recovery circuits under process variation.Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 1675-1680 More Information

Das S.;Li J.;Hossain A.;Nayak A.;Petriu E.;Biswas S.;Jone W. (09-15-2008. ) Improved test efficiency in cores-based system-on-chips using modelsim verification tool.Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 1487-1492 More Information

Das S.R.;Hossain A.;Biswas S.;Petriu E.M.;Assaf M.H.;Jone W.B.;Sahinoglu M. (08-12-2008. ) On a new graph theory approach to designing zero-aliasing space compressors for built-in self-testin.IEEE Transactions on Instrumentation and Measurement, , 57 (10 ) ,2146-2168 More Information

Xiong X.;Wu Y.;Jone W. (08-01-2008. ) Yield analysis for self-repairable MEMS devices.Analog Integrated Circuits and Signal Processing, , 56 (1-2 ) ,71-81 More Information

Liu J.;Jone W. (12-01-2007. ) An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects.2007 IEEE International Conference on Computer Design, ICCD 2007, , 360-367 More Information

Xiong X.;Wu Y.;Jone W. (12-01-2007. ) MEMS yield simulation with monte carlo method.Innovative Algorithms and Techniques in Automation, Industrial Electronics and Telecommunications, , 501-504 More Information

Pei W.;Jone W.B.;Hu Y.M. (12-01-2007. ) Fault modeling and detection for drowsy SRAM caches.Proceedings - International Test Conference, , More Information

Liu J.;Jone W.B.;Das S.R. (09-28-2007. ) Pseudo-exhaustive built-in self-testing of signal integrity for high-speed SoC interconnects .Conference Record - IEEE Instrumentation and Measurement Technology Conference, ,

Assaf M.H.;Das S.R.;Hermas W.;Jone W.B. (09-28-2007. ) Promising complex ASIC design verification methodology .Conference Record - IEEE Instrumentation and Measurement Technology Conference, ,

Pei W.;Jone W.;Hu Y. (06-01-2007. ) Fault modeling and detection for drowsy SRAM caches.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 26 (6 ) ,1084-1100 More Information

Das S.;Zakizadeh J.;Biswas S.;Assaf M.;Nayak A.;Petriu E.;Jone W.;Sahinoglu M. (06-01-2007. ) Testing analog and mixed-signal circuits with built-in hardware - A new approach.IEEE Transactions on Instrumentation and Measurement, , 56 (3 ) ,840-855 More Information

Cheng K.T.;Jone W.B.;Wang L.T. (12-01-2006. ) Test technology trends in the nanometer age.VLSI Test Principles and Architectures, , 679-749 More Information

Xiong X.;Wu Y.;Jone W. (12-01-2006. ) A self-repairable MEMS comb accelerometer.Advances in Computer, Information, and Systems Sciences, and Engineering - Proceedings of IETA 2005, TeNe 2005, EIAE 2005, , 75-82 More Information

Xiong X.;Wu Y.;Jone W. (12-01-2006. ) Reliability analysis of self-repairable MEMS accelerometer.Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, , 236-244 More Information

Martin R.;Jone W.;Das S. (12-01-2006. ) Fault detection and diagnosis for multi-level cell flash memories.Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 1896-1901 More Information

Li M.;Zeng Q.;Jone W. (12-01-2006. ) DyXY: A proximity congestion-aware deadlock-free dynamic routing method for network on chip.Proceedings - Design Automation Conference, , 849-852 More Information

Das S.;Mukherjee S.;Petriu E.;Assaf M.;Sahinoglu M.;Jone W. (12-01-2006. ) An improved fault simulation approach based on verilog with application to ISCAS benchmark circuits.Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 1902-1907 More Information

Das S.;Hossain A.;Petriu E.;Assaf M.;Sahinoglu M.;Jone W. (12-01-2006. ) On a new graph theory approach to designing zero-aliasing space compressors for built-in self-testin.Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 1890-1895 More Information

Li M.;Jone W.;Zeng Q. (10-09-2006. ) An efficient wrapper scan chain configuration method for Network-on-Chip testing.Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, , 2006 ,147-152 More Information

Liu J.;Jone W.;Das S. (08-01-2006. ) Crosstalk test pattern generation for dynamic programmable logic arrays.IEEE Transactions on Instrumentation and Measurement, , 55 (4 ) ,1288-1302 More Information

Xiong X.;Wu Y.;Jone W. (12-12-2005. ) Design and analysis of self-repairable MEMS accelerometer .Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, , 21-29

Liu J.;Jone W.;Das S. (12-01-2005. ) Crosstalk test pattern generation for dynamic programmable logic arrays.Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 1 ,55-60 More Information

Xiong X.;Wu Y.;Jone W. (12-01-2005. ) Yield analysis for self-repairable MEMS devices.Midwest Symposium on Circuits and Systems, , 2005 ,359-362 More Information

Lin C.H.;Huang Y.C.;Chang S.C.;Jone W.B. (12-01-2005. ) Design and design automation of rectification logic for engineering change .Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, , 2 ,1006-1009

Zakizadeh J.;Das S.;Assaf M.;Petriu E.;Sahinoglu M.;Jone W. (12-01-2005. ) Testing analog and mixed-signal circuits with built-in hardware - A new approach.Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 1 ,166-171 More Information

Das S.;Ramamoorthy C.;Assaf M.;Petriu E.;Jone W.;Sahinoglu M. (12-01-2005. ) Fault simulation and response compaction in full scan circuits using HOPE.IEEE Transactions on Instrumentation and Measurement, , 54 (6 ) ,2310-2328 More Information

Xiong X.;Wu Y.;Jone W. (10-01-2005. ) A dual-mode built-in self-test technique for capacitive MEMS devices.IEEE Transactions on Instrumentation and Measurement, , 54 (5 ) ,1739-1750 More Information

Narayanan V.;Ghosh S.;Jone W.;Das S. (10-01-2005. ) A built-in self-testing method for embedded multiport memory arrays.IEEE Transactions on Instrumentation and Measurement, , 54 (5 ) ,1721-1738 More Information

Das S.;Ramamoorthy C.;Assaf M.;Petriu E.;Jone W.;Sahinoglu M. (10-01-2005. ) Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using co.IEEE Transactions on Instrumentation and Measurement, , 54 (5 ) ,1662-1677 More Information

Min R.;Jone W.;Hu Y. (12-01-2004. ) Location cache: A low-power L2 cache system .Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04, , 120-125

Ghosh S.;Lai K.;Jone W.;Chang S. (12-01-2004. ) Scan chain fault identification using weight-based codes for SoC circuits .Proceedings of the Asian Test Symposium, , 210-215

Narayanan V.;Ghosh S.;Jone W.;Das S. (10-08-2004. ) A built-in self-testing method for embedded multiport memory arrays.Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 3 ,2027-2032 More Information

Das S.;Jin C.;Jin L.;Assaf M.;Petriu E.;Jone W.;Sahinoglu M. (10-08-2004. ) Implementation of a testing environment for digital IP cores.Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 2 ,1472-1477 More Information

Min R.;Jone W.;Hu Y. (09-07-2004. ) Phased tag cache: An efficient low power cache system .Proceedings - IEEE International Symposium on Circuits and Systems, , 2 ,

Arora V.;Jone W.;Huang D.;Das S. (08-01-2004. ) A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays.IEEE Transactions on Instrumentation and Measurement, , 53 (4 ) ,915-932 More Information

Xiong X.;Wu Y.;Jone W. (07-26-2004. ) A dual-mode built-in self-test technique for capacitive MEMS devices .Proceedings of the IEEE VLSI Test Symposium, , 148-153

Min R.;Xu Z.;Hu Y.;Jone W. (05-24-2004. ) Partial tag comparison: A new technology for power-efficient set-associative cache designs .Proceedings of the IEEE International Conference on VLSI Design, , 17 ,183-188

Min R.;Jone W.;Hu Y. (01-01-2004. ) Location Cache: A Low-Power L2 Cache System.Proceedings of the International Symposium on Low Power Electronics and Design, , 2004-January (January ) ,120-125 More Information

Jiang J.;Jone W.;Chang S.;Ghosh S. (12-01-2003. ) Embedded Core Test Generation Using Broadcast Test Architecture and Netlist Scrambling.IEEE Transactions on Reliability, , 52 (4 ) ,435-443 More Information

Jone W.;Huang D.;Das S. (10-01-2003. ) An efficient BIST method for non-traditional faults of embedded memory arrays.IEEE Transactions on Instrumentation and Measurement, , 52 (5 ) ,1381-1390 More Information

Das S.;Sudarma M.;Assaf M.;Petriu E.;Jone W.;Chakrabarty K.;?hino?lu M. (10-01-2003. ) Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with non.IEEE Transactions on Instrumentation and Measurement, , 52 (5 ) ,1363-1380 More Information

Arora V.;Jone W.;Huang D.;Das S. (07-11-2003. ) A parallel built-in self-diagnostic method for non-traditional faults of embedded memory arrays .Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 1 ,700-705

Das S.;Assaf M.;Petriu E.;Jone W. (07-11-2003. ) Revisiting response compaction in space for full scan circuits with nonexhaustive test sets using co .Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 1 ,693-699

Jone W.;Wang J.;Lu H.;Hsu I.;Chen J. (01-01-2003. ) Design theory and implementation for low-power segmented bus systems.ACM Transactions on Design Automation of Electronic Systems, , 8 (1 ) ,38-54 More Information

Jone W.;Huang D.;Wu S.;Lee K. (08-01-2002. ) An efficient BIST method for distributed small buffers.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 10 (4 ) ,512-514 More Information

Huang D.;Jone W. (05-01-2002. ) A parallel transparent BIST method for embedded memory arrays by tolerating redundant operations.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 21 (5 ) ,617-628 More Information

Huang D.;Jone W. (04-01-2002. ) A parallel built-in self-diagnostic method for embedded memory arrays.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 21 (4 ) ,449-465 More Information

Das S.;Liang J.;Petriu E.;Assaf M.;Jone W.;Chakrabarty K. (02-01-2002. ) Data compression in space under generalized mergeability based on concepts of cover table and freque.IEEE Transactions on Instrumentation and Measurement, , 51 (1 ) ,150-172 More Information

Jone W.;Huang D.;Das S. (01-01-2002. ) An efficient BIST method for non-traditional faults of embedded memory arrays.Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 1 ,601-606 More Information

Das S.;Assaf M.;Petriu E.;Jone W. (01-01-2002. ) Fault simulation and response compaction in full scan circuits using HOPE .Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 1 ,607-612

Das S.;Ramamoorthy C.;Assaf M.;Petriu E.;Jone W. (12-01-2001. ) Fault tolerance in systems design in VLSI using data compression under constraints of failure probab.IEEE Transactions on Instrumentation and Measurement, , 50 (6 ) ,1725-1747 More Information

Jone W.;Yeh W.;Yeh C.;Das S. (10-01-2001. ) An adaptive path selection method for delay testing.IEEE Transactions on Instrumentation and Measurement, , 50 (5 ) ,1109-1118 More Information

Chang S.;Cheng C.;Jone W.;Lee S.;Wang J. (02-01-2001. ) Charge-sharing alleviation and detection for CMOS domino circuits.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 20 (2 ) ,266-280 More Information

Jiang J.;Jone W.;Chang S. (01-01-2001. ) Embedded core testing using broadcast test architecture.IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, , 95-103 More Information

Huang D.;Jone W.;Das S. (01-01-2001. ) An efficient parallel transparent BIST method for multiple embedded memory buffers .Proceedings of the IEEE International Conference on VLSI Design, , 379-384

Huang D.;Jone W.;Das S. (01-01-2001. ) A parallel built-in self-diagnostic method for embedded memory buffers .Proceedings of the IEEE International Conference on VLSI Design, , 397-402

Jone W.;Huang D.;Chang S.;Das S. (01-01-2001. ) Defect level estimation for pseudorandom testing using stochastic analysis.VLSI Design, , 12 (4 ) ,457-474 More Information

Das S.;Assaf M.;Petriu E.;Jone W.;Chakrabarty K. (01-01-2001. ) A novel approach to designing aliasing-free space compactors based on switching theory formulation.Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 1 ,198-203 More Information

Huang D.;Jone W. (12-01-2000. ) Efficient parallel transparent diagnostic BIST .Proceedings of the Asian Test Symposium, , 299-303

Cheng C.;Jone W.;Wang J.;Chang S. (12-01-2000. ) Low-speed scan testing of charge-sharing faults for CMOS domino circuits .IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, , 329-337

Cheng C.;Jone W.;Wang J.;Chang S. (12-01-2000. ) Charge sharing fault analysis and testing for CMOS domino logic circuits .Proceedings of the Asian Test Symposium, , 435-440

Cheng C.;Jone W.;Chang S.;Wang J. (09-28-2000. ) Low-speed scan testing of charge-sharing faults for CMOS domino circuits.Electronics Letters, , 36 (20 ) ,1684-1685 More Information

Rau J.;Jone W.;Chang S.;Wu Y. (09-01-2000. ) Tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits.IEE Proceedings: Computers and Digital Techniques, , 147 (5 ) ,343-348 More Information

Chang S.;Jone W.;Chang S. (01-01-2000. ) TAIR: Testability analysis by implication reasoning.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 19 (1 ) ,152-160 More Information

Chang S.; Jone W.; Lee K.; Wu Z. (01-01-2000. ) Reducing test application time by scan flip-flops sharing.IEE Proceedings: Computers and Digital Techniques, , 147 (1 ) ,42-48 More Information

Cheng C.;Chang S.;Li S.;Jone W.;Wang J. (01-01-2000. ) Synthesis of CMOS domino circuits for charge sharing alleviation.IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, , 2000-January ,387-390 More Information

Das S.;Liang J.;Petriu E.;Jone W.;Chakrabarty K. (01-01-2000. ) Data compression in space under generalized mergeability based on concepts of cover table and freque .Conference Record - IEEE Instrumentation and Measurement Technology Conference, , 1 ,217-222

Das S.;Sudarma M.;Liang J.;Petriu E.;Assaf M.;Jone W. (01-01-2000. ) Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with com.Midwest Symposium on Circuits and Systems, , 1 ,198-201 More Information

Cheng C.;Chang S.;Wang J.;Jone W. (12-01-1999. ) Charge sharing fault detection for CMOS domino logic circuits .IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, , 77-85

Chen J.;Jone W.;Wang J.;Lu H.;Chen T. (12-01-1999. ) Segmented bus design for low-power systems.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 7 (1 ) ,25-29 More Information

Cheng C.;Chang S.;Wang J.;Jone W. (01-01-1999. ) Charge sharing fault detection for CMOS domino logic circuits.Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999, , 77-85 More Information

Chang M.; Chang S.; Jone W.; Yeh C. (01-01-1999. ) Power reduction through iterative gate sizing and voltage scaling .Proceedings - IEEE International Symposium on Circuits and Systems, , 1 ,

Jone W.;Huang D.;Wu S.;Lee K. (01-01-1999. ) Efficient BIST method for small buffers .Proceedings of the IEEE VLSI Test Symposium, , 246-251

Chang M.; Chang S.; Jone W.; Yeh C. (01-01-1999. ) Gate-level design exploiting dual supply voltages for power-driven applications .Proceedings - Design Automation Conference, , 68-71

Jone W.;Rau J.;Chang S.;Wu Y. (12-01-1998. ) Tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits .IEEE International Test Conference (TC), , 322-330

Chang S.C.;Chang S.S.;Jone W.B.;Tsai C.C. (12-01-1998. ) Novel combinational testability analysis by considering signal correlation.IEEE International Test Conference (TC), , 658-667 More Information

Jone W.;Tsai K. (01-01-1998. ) Confidence analysis for defect-level estimation of vlsi random testing.ACM Transactions on Design Automation of Electronic Systems, , 3 (3 ) ,389-407 More Information

Jone W.;Das S. (01-01-1998. ) Stochastic method for defect level analysis of pseudorandom testing .Proceedings of the IEEE International Conference on VLSI Design, , 382-385

Das S.;Goel N.;Jone W.;Nayak A. (01-01-1998. ) Syndrome signature in output compaction for VLSI built-in self-test.VLSI Design, , 7 (2 ) ,191-201 More Information

Jone W.;Ho Y.;Das S. (01-01-1997. ) Delay Fault Coverage Enhancement Using Variable Observation Times.Journal of Electronic Testing: Theory and Applications (JETTA), , 11 (2 ) ,131-146 More Information

Jone W.;Ho Y.;Das S. (01-01-1997. ) Delay fault coverage enhancement using multiple test observation times .Proceedings of the IEEE International Conference on VLSI Design, , 106-110

Das S.;Nayak A.;Assaf M.;Jone W. (01-01-1997. ) Realizing ultimate compression with acceptable fault coverage degradation to reduce MISR size in BIS .Proceedings - IEEE International Symposium on Circuits and Systems, , 4 ,2717-2720

Li D.;Jone W. (12-01-1996. ) Pseudorandom test-length analysis using differential solutions.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 15 (7 ) ,815-825 More Information

Jone W.;Shah N.;Gleason A.;Das S. (01-01-1996. ) PGEN: A Novel Approach to Sequential Circuit Test Generation.VLSI Design, , 4 (3 ) ,149-165 More Information

Das S.;Goel N.;Jone W.;Nayak A. (01-01-1996. ) Syndrome signature in output compaction for VLSI BIST .Proceedings of the IEEE International Conference on VLSI Design, , 337-338

Jone W. (01-01-1995. ) CACOP—A Random Pattern Testability Analyzer.IEEE Transactions on Systems, Man, and Cybernetics, , 25 (5 ) ,865-871 More Information

Jone W. (01-01-1995. ) A Coordinated Circuit Partitioning and Test Generation Method for Pseudo-Exhaustive Testing of VLSI .IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 14 (3 ) ,374-384 More Information

Fang C.;Jone W. (01-01-1995. ) Timing Optimization by Gate Resizing and Critical Path Identification.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 14 (2 ) ,201-217 More Information

Jone W.;Gondalia P.;Gutjahr A. (01-01-1995. ) Realizing a High Measure of Confidence for Defect Level Analysis of Random Testing.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 3 (3 ) ,446-450 More Information

Das S.;Choi I.;Jone W.;Nayak A. (01-01-1995. ) On Testing of Sequential Machines Using Circuit Decomposition and Stochastic Modeling.IEEE Transactions on Systems, Man, and Cybernetics, , 25 (3 ) ,489-504 More Information

Das S.; Ho H.; Jone W. (12-01-1994. ) Modified dynamic space compression for built-in self-testing of VLSI circuits .Midwest Symposium on Circuits and Systems, , 1 ,217-224

Nayak A.;Jone W.;Das S. (12-01-1994. ) Designing general-purpose fault-tolerant distributed systems - a layered approach .Proceedings of the Internatoinal Conference on Parallel and Distributed Systems - ICPADS, , 360-364

Jone W. (01-01-1994. ) Multiple Fault Detection in Parity Checkers.IEEE Transactions on Computers, , 43 (9 ) ,1096-1099 More Information

Das S.;Jone W.;Nayak A.;Choi I. (01-01-1994. ) On probabilistic testing of large-scale sequential circuits using circuit decomposition .Proceedings of the IEEE International Conference on VLSI Design, , 311-314

Gondalia P.;Gutjahr A.;Jone W. (12-01-1993. ) Realizing a high measure of confidence for defect level analysis of random testing .Proceedings of the International Test Conference, , 478-487

Jone W. (01-01-1993. ) Defect Level Estimation of Circuit Testing Using Sequential Statistical Analysis.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 12 (2 ) ,336-348 More Information

Jone W.;Fang C. (01-01-1993. ) Timing optimization by gate resizing and critical path identification .Proceedings - Design Automation Conference, , 135-139

Wu C.J.;Jone W.B. (01-01-1993. ) On multiple fault detection of parity checkers .Proceedings - IEEE International Symposium on Circuits and Systems, , 3 ,1515-1518

Jone W. (01-01-1992. ) Defect level estimation of random and pseudorandom testing .Digest of Papers - International Test Conference, , 712-721

Das S.; Jone W. (01-01-1992. ) On Random Testing for Combinational Circuits with a High Measure of Confidence.IEEE Transactions on Systems, Man and Cybernetics, , 22 (4 ) ,748-754 More Information

Gleason A.;Jone W. (12-01-1991. ) Counter reduction techniques for Hamming count .Proceedings - IEEE International Symposium on Circuits and Systems, , 4 ,1980-1983

Gleason A.;Jone W. (12-01-1991. ) Reduced Hamming count and its aliasing probability .IEEE International Conference on Computer Design - VLSI in Computers and Processors, , 356-359

Jone W.;Gleason A. (11-01-1991. ) Analysis of Hamming count compaction scheme.Journal of Electronic Testing, , 2 (4 ) ,373-384 More Information

Jone W. (12-01-1990. ) DSC--A space compression method .Proceedings - IEEE International Symposium on Circuits and Systems, , 4 ,2756-2759

Jone W.;Das S. (05-01-1990. ) Multiple-output parity bit signature for exhaustive testing.Journal of Electronic Testing, , 1 (2 ) ,175-178 More Information

Das S.;Jone W.;Wong K. (01-01-1990. ) Probabilistic Modeling and Fault Analysis in Sequential Logic Using Computer Simulation.IEEE Transactions on Systems, Man and Cybernetics, , 20 (2 ) ,490-498 More Information

Jone W.;Papachristou C. (12-01-1989. ) Coordinated approach to partitioning and test pattern generation for pseudoexhaustive testing .Proceedings - Design Automation Conference, , 525-530

Gleason A.;Jone W. (12-01-1989. ) Hamming count - A compaction testing technique .Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, , 344-347

Jone W.;Papachristou C.;Pereira M. (12-01-1989. ) Scheme for overlaying concurrent testing of VLSI circuits .Proceedings - Design Automation Conference, , 531-536

Das S.; Fares G.; Jone W.; Nayak A. (01-01-1989. ) Probabilistic fault location in combinational logic network using concepts of fault distance and inp.Cybernetics and Systems, , 20 (5 ) ,385-399 More Information

Jone W.;Papachristou C. (12-01-1988. ) On partitioning for pseudo exhaustive testing of VLSI circuits .Proceedings - IEEE International Symposium on Circuits and Systems, , 2 ,1843-1846

Chiang K.; Das S.; Jone W. (01-01-1987. ) A First-order optimal algorithm for state identification in sequential logic using the concept of en.Cybernetics and Systems, , 18 (3 ) ,251-270 More Information

Das S.; Jone W. (01-01-1986. ) Modified transition matrix and fault testing in sequential logic circuits under random stimuli with .Cybernetics and Systems, , 17 (1 ) ,1-12 More Information

Chen Z.; Hsu W.; Jone W.; R. Das S. (01-01-1986. ) Further studies on the matrix approach to the measurement and control problems of synchronous sequen.Computers and Electrical Engineering, , 12 (3-4 ) ,161-173 More Information

Chen Z.; Das S.; Jone W.; Lee S.; Lee T.; Nath A. (12-01-1982. ) FAULT LOCATION IN COMBINATIONAL LOGIC NETWORKS BY MULTISTAGE BINARY TREE CLASSIFIER. Proceedings - IEEE International Conference on Circuits and Computers, , 624-628

Keywords

VLSI design for testability and reliability, low-power circuit design and test, error-resilient circuit design and test, and multi-core computer architecture and parallel program debugging, and VLSI design for deep learning.

Other Information

https://scholar.google.com/scholar?hl=en&as_sdt=0,36&q=%22WB+Jone%22,