Ranganadha Vemuri

Ranganadha Vemuri

Professor

Engineering Research Cntr

530

CEAS - Elec Eng & Computer Science - 0030

Professional Summary

Dr. Ranga Vemuri has been on the faculty of Electrical and Computer Engineering at University of Cincinnati since 1989 and is currently a Professor. 

His interests span various topics within Hardware Trust, Correctness and Security; VLSI Design and Architectures; Embedded Systems, Cyber-Physical Systems and Applications; Formal Methods and Formal Verification; Electronic Design Automation, Logic and Physical Synthesis; Reconfigurable Computing and FPGAs; Approximate Computing; Sensor Networks.

He and his students have published over 250 papers.  Dr. Vemuri graduated over 40 PhD and 60 MS students. 

His reseach has been funded by AFRL, DARPA, NSF, SRC, State of Ohio and various industries including EDAptive Computing Inc..

Education

Ph.D, Case Western Reserve University Cleveland, 1988 (Computer Engineering)

M.Tech., Indian Institute of Technology Kharagpur, India, 1984 (Computer Engineering)

B.Tech., Nagarjuna University India, 1983 (Electronics and Communications Engineering)

Research and Practice Interests

VLSI Design, Design Automation of Digital, Analog and Mixed Signal Systems, Reconfigurable Architectures, Hardware Security and Side-Channel Attacks, Formal Methods and Verification
 

Research Support

Grant: #OBR AF 749 Investigators:Vemuri, Ranganadha 09-01-2004 -08-31-2007 Ohio Board of Regents Acquisition of Research Equipment for Electronic Systems Emulation, Prototyping and Testing Role:PI $60,000.00 Closed Level:State of Ohio

Grant: #CNS-0421092 Investigators:Vemuri, Ranganadha 09-01-2004 -08-31-2008 National Science Foundation Acquisition of Research Equipment for Electronic Systems Emulation, Prototyping and Testing Role:PI $280,085.00 Closed Level:Federal

Grant: #CCF-0429717 Investigators:Vemuri, Ranganadha 08-15-2004 -07-31-2008 National Science Foundation Performance Macromodeling for Synthesis of Electronic Systems Role:PI $224,960.00 Closed Level:Federal

Grant: #FY2004-0903-08 Investigators:Vemuri, Ranganadha 07-01-2003 -06-01-2004 Ohio Arts Council Indian Classical Music and Dance Role:PI $2,918.00 Closed Level:State of Ohio

Grant: #S00-001UC/Mod Investigators:Vemuri, Ranganadha 10-20-2000 -09-20-2002 Department of the Air Force Genetic Partitioning Role:PI $129,800.00 Closed Level:Federal

Grant: #FY2000-917-08 Investigators:Vemuri, Ranganadha 07-01-1999 -06-30-2000 Ohio Arts Council Indian Classical Music and Dance Role:PI $4,629.00 Closed Level:State of Ohio

Grant: #IF-UC-00-07 Investigators:Vemuri, Ranganadha 04-03-2000 -03-31-2003 Ohio Board of Regents Application Accelerating Reconfigurable Computer Role:PI $249,768.00 Closed Level:State of Ohio

Grant: #SN-UC-01-08 Investigators:Vemuri, Ranganadha 07-01-2001 -06-30-2004 Ohio Board of Regents Mixed Signal Synthesis Role:PI $166,920.00 Closed Level:State of Ohio

Grant: #F3361501C1977/P00004 Investigators:Vemuri, Ranganadha 06-19-2001 -10-31-2004 Department of the Air Force Design Automation for High Performance Analog Systems Role:PI $1,150,000.00 Closed Level:Federal

Grant: #WC104-010-UC-1 Investigators:Vemuri, Ranganadha 10-27-2003 -06-30-2009 Ohio Department of Development Wright Center of Innovation for Advanced Data Management and Analysis Role:PI $449,986.00 Closed Level:State of Ohio

Grant: #F3361596C1911/P00009 Investigators:Vemuri, Ranganadha 09-13-1996 -09-30-2001 Department of the Air Force Synthesis of Mixed-Signal Systems Role:PI $513,000.00 Closed Level:Federal

Grant: #DABT6396C0051/P00004 Investigators:Vemuri, Ranganadha 09-10-1996 -09-09-1999 Department of the Army Techniques for Ultra Large Scale Hardware Verification Role:PI $209,844.00 Closed Level:Federal

Grant: #CDA-9634462-001 Investigators:Vemuri, Ranganadha 08-15-1996 -07-31-2002 National Science Foundation Integration of High Level Synthesis, Analysis and Test Generation Research Results into Undergraduate Minor Curriculum in VLSI Systems Role:PI $249,042.00 Closed Level:Federal

Grant: #DABT6397C0030/P00001 Investigators:Vemuri, Ranganadha 07-01-1997 -10-31-2000 Advanced Research Projects Agency The Comprehensive Analysis of Adaptive Computing Systems Role:PI $619,635.00 Closed Level:Federal

Grant: #F3361597C1043/P00008 Investigators:Vemuri, Ranganadha 07-25-1997 -09-30-2001 Department of the Air Force Synthesis of Reconfigurable Architectures Role:PI $698,000.00 Closed Level:Federal

Grant: #S99-001-UC/Mods 1,2 Investigators:Vemuri, Ranganadha 01-04-1999 -01-03-2001 Department of the Army Systems on a Chip Created Using Extended Requirements Language - Phase II Role:PI $50,015.00 Closed Level:Federal

Grant: #ECA - Master for 11 Students Investigators:Agrawal, Dharma; Bakshi, Arjun; Berman, Kenneth; Bhatnagar, Raj; Bhattacharya, Prabir; Borowczak, Mike; Chaganti, Shikha; Davis, Karen; Guo, Minzhe; Helmicki, Arthur; Kohram, Mojtaba; Li, Hailong; Mukherjee, Tuhin; Ralescu, Anca; Ren, Zhaowei; Tan, Lirong; Vemuri, Ranganadha; Wu, Chao; Zhu, Cheng 09-01-2012 -08-31-2013 Cincinnati Children's Hospital Medical Center Education Collaboration Agreement with CCHMC - 11 Students Role:Collaborator $246,693.00 Active Level:Private Non-Profit

Grant: #SETS03-UC-2017 / USAF FA8650-14-D-1724/0003 Investigators:Jha, Rashmi; Vemuri, Ranganadha 02-01-2018 -01-30-2019 Air Force Research Laboratory Secure Engineering of Trusted Systems (SETS), USAF FA8650-14-D-1724/0003 Role:PI $102,500.00 Active Level:Federal

Grant: #SETS08-UC-2017 / AFRL Prime Contract FA8650-14-D-1724/FA8650-17-F-1034 Investigators:Vemuri, Ranganadha 06-07-2017 -11-01-2020 Air Force Research Laboratory Trust in Integrated Circuits - Application of REVEAL Role:PI $358,037.00 Awarded Level:Federal

Grant: #RY3-UC-18-6-AFRL_Fellowship_Chuvalas Investigators:Vemuri, Ranganadha 07-01-2018 -12-31-2019 Air Force Research Laboratory Hardware Acceleration of Assessment Tools for Trusted Microelectronics Role:PI $51,925.00 Active Level:Federal

Grant: #SETS04-UC-2019 / FA8650-14-D-1724/0004 Investigators:Emmert, John; Jha, Rashmi; Vemuri, Ranganadha 06-01-2019 -04-30-2020 Air Force Research Laboratory Secure Engineering of Trusted Systems (SETS 04) Role:Collaborator $932,517.00 Awarded Level:Federal

Grant: #STAMP01-UC/MAA-2018 (A-8) / FA8650-18-F-1613 Investigators:Bhatnagar, Raj; Minai, Ali; Niu, Nan; Ralescu, Anca; Vemuri, Ranganadha 08-26-2019 -12-28-2019 Air Force Research Laboratory Exhibit A-8: Application and research into using ML analytics to evaluate/improve verification test processes and results Role:Collaborator $123,689.40 Awarded Level:Federal

Grant: #IMPACT02-UC-02-2020 / AFRL - W911QY-17-C-0114 Investigators:Vemuri, Ranganadha 01-02-2020 -08-25-2020 Air Force Research Laboratory A Platform for Obfuscation of Hardware Designs Role:PI $175,000.00 Awarded Level:Federal

Grant: #IMPACT02-UC-03-2020 / AFRL - W911QY-17-C-0114 Investigators:Vemuri, Ranganadha 01-02-2020 -08-25-2020 Air Force Research Laboratory SoC Trust Validation Using Formal Security Assertions Role:PI $175,000.00 Awarded Level:Federal

Grant: #STAMP02-UC/MAA-2018 (A-9) / FA8650-20-F-1956 Investigators:Bhatnagar, Raj; Minai, Ali; Niu, Nan; Vemuri, Ranganadha 12-29-2019 -05-02-2020 Air Force Research Laboratory Exhibit A-9: Application and research into using ML analytics to evaluate/improve verification test processes and results Role:Collaborator $98,661.80 Awarded Level:Federal

Grant: #STAMP02-UC/MAA-2018 / Exh A-10_FA8650-20-F-1956 Investigators:Bhatnagar, Raj; Minai, Ali; Niu, Nan; Vemuri, Ranganadha 05-03-2020 -08-22-2020 Air Force Research Laboratory Application and research into using ML analytics to evaluate/improve verification test processes and results Role:Collaborator $114,519.08 Awarded Level:Federal

Publications

Peer Reviewed Publications

Doboli A.;Vemuri R. (12-01-2000. ) Towards a specification notation for high-level synthesis of mixed-signal and analog systems.2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, , 109-116

Chatha K.;Vemuri R. (01-01-2001. ) MAGELLAN: Multiway hardware-software partitioning and scheduling for latency minimization of hierarc .Hardware/Software Codesign - Proceedings of the International Workshop, , 42-47

Ganesan S.;Vemuri R. (01-01-2001. ) Behavioral partitioning in the synthesis of mixed analog-digital systems .Proceedings - Design Automation Conference, , 133-138

Doboli A.;Vemuri R. (01-01-2001. ) Integrated high-level synthesis and power-net routing for digital design under switching noise const.Proceedings - Design Automation Conference, , 629-634

Ganesan S.;Vemuri R. (01-01-2001. ) Library binding for high-level synthesis of analog systems .Proceedings of the IEEE International Conference on VLSI Design, , 261-268

Doboli A.;Vemuri R. (01-01-2001. ) Hierarchical performance optimization for synthesis of linear analog systems .ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, , 5 ,431-434

Sundararaman S.;Govindarajan S.;Vemuri R. (01-01-2001. ) Application specific macro based synthesis.Proceedings of the IEEE International Conference on VLSI Design, , 317-324

Vemuri R.;Gupta R. (02-01-2001. ) Guest editorial: Reconfigurable and adaptive VLSI systems.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 9 (1 ) ,107-108

Srinivasan V.;Govindarajan S.;Vemuri R. (02-01-2001. ) Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and des.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 9 (1 ) ,140-158

Narasimhan N.;Teica E.;Radhakrishnan R.;Govindarajan S.;Vemuri R. (01-01-2001. ) Theorem proving guided development of formal assertions in a resource-constrained scheduler for high.Formal Methods in System Design, , 19 (3 ) ,237-273

Doboli A.;Vemuri R. (11-01-2001. ) A regularity-based hierarchical symbolic analysis method for large-scale analog networks.IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, , 48 (11 ) ,1054-1068

Vemuri R.;Katkoori S.;Kaul M.;Roy J. (01-01-2002. ) An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral s.ACM Transactions on Design Automation of Electronic Systems, , 7 (1 ) ,189-216

Chatha K.;Vemuri R. (06-01-2002. ) Hardware-software partitioning and pipelined scheduling of transformative applications.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 10 (3 ) ,193-208

Wolfe G.;Vemuri R. (02-01-2003. ) Extraction and use of neural network models in automated synthesis of operational amplifiers.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 22 (2 ) ,198-212

Ganesan S.;Vemuri R. (12-01-2000. ) An integrated temporal partitioning and partial reconfiguration technique for design latency improve.Proceedings -Design, Automation and Test in Europe, DATE, , 320-325

Doboli A.;Vemuri R. (12-01-2002. ) A functional specification notation for co-design of mixed analog-digital systems.Proceedings -Design, Automation and Test in Europe, DATE, , 760-767

Doboli A.;Vemuri R. (11-01-2003. ) Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 22 (11 ) ,1504-1520

Doboli A.;Vemuri R. (11-01-2003. ) Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 22 (11 ) ,1556-1568

Mukherjee M.;Vemuri R. (12-02-2003. ) A novel synthesis strategy driven by partial evaluation based circuit reduction for application spec .Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, , 436-440

Mukherjee M.;Vemuri R. (12-01-2004. ) A methodology for performance driven incremental placement with high level exploration .Midwest Symposium on Circuits and Systems, , 1 ,

Bhaduri A.;Vijay V.;Agarwal A.;Vemuri R.;Mukherjee B.;Wang P.;Pacelli A. (12-01-2004. ) Parasitic-aware synthesis of RF LNA circuits considering quasi-static extraction of inductors and in .Midwest Symposium on Circuits and Systems, , 1 ,

Handa M.;Vemuri R. (12-01-2004. ) Hardware assisted two dimensional ultra fast placement .Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM), , 18 ,1915-1922

Huang R.;Vemuri R. (12-01-2004. ) Forward-looking macro generation and relational placement during high level synthesis to FPGAs .Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM), , 18 ,1893-1898

Khan J.;Sethuraman B.;Vemuri R. (12-01-2004. ) A power-performance trade-off methodology for portable reconfigurable platforms .Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04, , 33-37

Jia X.;Vemuri R. (12-01-2004. ) A design methodology for self-timed event logic pipelines .Proceedings of the International Conference on Embedded Systems and Applications ESA'04 - Proceedings of the International Conference on VLSI, VLSI'04, , 475-479

Handa M.;Vemuri R. (12-01-2004. ) Area fragmentation in reconfigurable operating systems .Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04, , 77-83

Khan J.;Rajagopalan J.;Huang R.;Vemuri R. (12-01-2004. ) A portable face recognition system using reconfigurable hardware .Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04, , 213-217

Sethuraman B.;Khan J.;Vemuri R. (12-01-2004. ) Battery-efficient task execution on portable reconfigurable computing platforms .Proceedings - IEEE International SOC Conference, , 237-240

Ranjan M.;Bhaduri A.;Verhaegen W.;Mukherjee B.;Vemuri R.;Gielen G.;Pacelli A. (12-01-2004. ) Use of symbolic performance models in layout-inclusive RF low noise amplifier synthesis .BMAS 2004 - Proceedings of the 2004 IEEE International Behavioral Modeling and Simulation Conference, , 130-134

Wolfe G.;Vemuri R. (12-01-2004. ) Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines.IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, , 931-938

Huang R.;Vemuri R. (12-01-2004. ) Analysis and evaluation of a hybrid interconnect structure for FPGAs .IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, , 595-601

Mukherjee M.;Vemuri R. (12-01-2004. ) Simultaneous scheduling, binding and layer assignment for synthesis of vertically integrated 3D syst.Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, , 222-227

Ouaiss I.;Vemuri R. (01-01-2001. ) Global memory mapping for FPGA-based reconfigurable systems.Proceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001, , 1473-1480

Yang H.;Agarwal A.;Vemuri R. (10-25-2005. ) Fast analog circuit synthesis using multiparameter sensitivity analysis based on element-coefficient.Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI, , 71-76

Huang R.;Vemuri R. (10-25-2005. ) Sensitivity analysis of a cluster-based interconnect model for FPGAs .Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI, , 250-251

Khan J.;Vemuri R. (12-01-2005. ) An iterative algorithm for battery - A ware task scheduling on portable computing platforms.Proceedings -Design, Automation and Test in Europe, DATE '05, , I ,622-628

Ranganathan N.;Agrawal V.;Chakradhar S.;Chakrabarty K.;Courtois B.;DeMara R.;Hu X.;Ismail Y.;Jha N.;John L.;Ker M.;Koren I.;Liu B.;Marculescu D.;Marculescu R.;Narayanan V.;Nassif S.;Nowick S.;Sapatnekar S.;Sherlekar S.;Sylvester D.;Vemuri R.;Pham M. (07-01-2005. ) Appointments for 2005-2006 term.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 13 (7 ) ,773-782

Ding M.;Vemuri R. (12-01-2005. ) A combined feasibility and performance macromodel for analog circuits .Proceedings - Design Automation Conference, , 63-68

Huang R.;Vemuri R. (12-01-2005. ) On-line synthesis for partially reconfigurable FPGAs.Proceedings of the IEEE International Conference on VLSI Design, , 663-668

Ding M.;Vemuri R. (12-01-2005. ) An active learning scheme using support vector machines for analog circuit feasibility classificatio .Proceedings of the IEEE International Conference on VLSI Design, , 528-534

Mukherjee M.;Vemuri R. (12-01-2005. ) On physical-aware synthesis of vertically integrated 3D systems.Proceedings of the IEEE International Conference on VLSI Design, , 647-652

Bhaduri A.;Vemuri R. (12-29-2005. ) Moment-driven coupling-aware routing methodology .Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, , 390-395

Sethuraman B.;Bhattacharya P.;Khan J.;Vemuri R. (12-29-2005. ) LiPaR: A light-weight parallel router for FPGA-based networks-on-chip .Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, , 452-457

Agarwal A.;Wolfe G.;Vemuri R. (12-29-2005. ) Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits .Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, , 482-487

Doboli A.;Dhanwada N.;Nunez-Aldana A.;Vemuri R. (04-01-2004. ) A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications.ACM Transactions on Design Automation of Electronic Systems, , 9 (2 ) ,238-271

Badaoui R.F.;Sampath H.;Agarwal A.;Vemuri R. (06-28-2004. ) A high level language for pre-layout extraction in parasite-aware analog circuit synthesis .Proceedings of the ACM Great Lakes Symposium on VLSI, , 271-276

Doboli A.;Vemuri R. (01-01-2001. ) Fast evaluation of digital switching noise for synthesis of mixed-signal applications.Proceedings of the IEEE International Workshop on Behavioral Modeling and Simulation, BMAS, , 2001-January ,32-37

Handa M.;Vemuri R. (07-12-2004. ) A fast algorithm for finding maximal empty rectangles for dynamic FPGA placement.Proceedings - Design, Automation and Test in Europe Conference and Exhibition, , 1 ,744-745

Ranjan M.;Verhaegen W.;Agarwal A.;Sampath H.;Vemuri R.;Gielen G. (07-12-2004. ) Fast, layout-inclusive analog circuit synthesis using pre-compiled parasitic-aware symbolic performa.Proceedings - Design, Automation and Test in Europe Conference and Exhibition, , 1 ,604-609

Agarwal A.;Sampath H.;Yelamanchili V.;Vemuri R. (07-12-2004. ) Accurate estimation of parasitic capacitances in analog circuits.Proceedings - Design, Automation and Test in Europe Conference and Exhibition, , 2 ,1364-1365

Dhanwada N.;Doboli A.;Nunez-Aldana A.;Vemuri R. (06-01-2006. ) Hierarchical constraint transformation based on genetic optimization for analog system synthesis.Integration, the VLSI Journal, , 39 (3 ) ,267-290

Bhaduri A.;Vemuri R. (12-01-2005. ) Inductive and capacitive coupling aware routing methodology driven by a higher order RLCK moment met.Proceedings -Design, Automation and Test in Europe, DATE '05, , II ,922-923

Badaoui R.;Vemuri R. (12-01-2005. ) Multi-placement structures for fast and optimized placement in analog circuit synthesis.Proceedings -Design, Automation and Test in Europe, DATE '05, , I ,138-143

Ding M.;Vemuri R. (12-01-2005. ) A two-level modeling approach to analog circuit performance macromodeling.Proceedings -Design, Automation and Test in Europe, DATE '05, , II ,1088-1089

Jia X.;Vemuri R. (12-01-2005. ) The GAPLA: A globally asynchronous locally synchronous FPGA architecture.Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005, , 2005 ,291-292

Khan J.;Vemuri R. (12-01-2005. ) Battery-efficient task execution on reconfigurable computing platforms with multiple processing unit.Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005, , 2005 ,

Khan J.;Vemuri R. (12-01-2005. ) Energy management in battery-powered sensor networks with reconfigurable computing nodes.Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL, , 2005 ,543-546

Jia X.;Vemuri R. (12-01-2005. ) A novel asynchronous FPGA architecture design and its performance evaluation.Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL, , 2005 ,287-292

Huang R.;Vemuri R. (12-01-2005. ) Pahls: Towards run-time synthesis for FPGAs.Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL, , 2005 ,739-740

Jia X.;Vemuri R. (12-01-2005. ) Using GALS architecture to reduce the impact of long wire delay on FPGA performance .Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, , 2 ,1260-1263

Jia X.;Vemuri R. (09-18-2006. ) CAD tools for a globally asynchronous locally synchronous FPGA architecture.Proceedings of the IEEE International Conference on VLSI Design, , 2006 ,251-256

Ding M.;Vemuri R. (09-18-2006. ) Efficient analog performance macromodeling via sequential design space decomposition.Proceedings of the IEEE International Conference on VLSI Design, , 2006 ,553-556

Agarwal A.;Vemuri R. (12-01-2005. ) Layout-aware RF circuit synthesis driven by worst case parasitic corners.Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, , 2005 ,444-449

Chakraborty R.;Ranjan M.;Vemuri R. (09-18-2006. ) Symbolic time-domain behavioral and performance modeling of linear analog circuits using an efficien.Proceedings of the IEEE International Conference on VLSI Design, , 2006 ,689-694

Bhaduri A.;Vemuri R. (09-18-2006. ) Parasitic aware routing methodology based on higher order RLCK moment metrics.Proceedings of the IEEE International Conference on VLSI Design, , 2006 ,141-146

Sundaresan V.;Vemuri R. (10-09-2006. ) A novel approach to performance-oriented datapath allocation and floorplanning.Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, , 2006 ,323-328

Huang R.;Vemuri R. (11-16-2006. ) Transformation synthesis for data intensive applications to FPGAs .Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, , 2006 ,349-352

Agarwal A.;Vemuri R. (12-01-2005. ) Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits.IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, , 2005 ,429-435

Sundaresan V.;Radhakrishnan R.;Siva S.;Vemuri R. (12-01-2005. ) Symbolic verification of synthesized RTL using boolean satisfiability and uninterpreted RTL transfor.Midwest Symposium on Circuits and Systems, , 2005 ,99-103

Sethuraman B.;Vemuri R. (12-01-2006. ) OptiMap: A tool for automated generation of NoC architectures using multi-port routers for FPGAs .Proceedings -Design, Automation and Test in Europe, DATE, , 1 ,

Yang H.;Vemuri R. (12-01-2006. ) Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in .Proceedings -Design, Automation and Test in Europe, DATE, , 1 ,

Khan J.;Handa M.;Vemuri R. (12-01-2002. ) iPACE-V1: A portable adaptive computing engine for real time applications .Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 2438 LNCS ,69-78

Ranjan M.;Vemuri R. (12-01-2006. ) Exact hierarchical symbolic analysis of large analog networks using a general interconnection templa .Proceedings - IEEE International Symposium on Circuits and Systems, , 1776-1779

Basu S.;Thakore P.;Vemuri R. (08-28-2007. ) Process variation tolerant standard cell library development using reduced dimension statistical mod.Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007, , 814-820

Handa M.;Radhakrishnan R.;Mukherjee M.;Vemuri R. (01-01-2003. ) A fast macro based compilation methodology for partially reconfigurable FPGA designs.Proceedings of the IEEE International Conference on VLSI Design, , 2003-January ,91-96

Das A.;Vemuri R. (09-27-2007. ) GAPSYS: A GA-based tool for automated passive analog circuit synthesis .Proceedings - IEEE International Symposium on Circuits and Systems, , 2702-2705

Bhaduri A.;Vemuri R. (12-01-2006. ) Parasitic-aware and moment-driven constraint satisfying non-linear routing methodology.Midwest Symposium on Circuits and Systems, , 2 ,84-88

Khan J.;Vemuri R. (12-01-2004. ) An efficient battery-aware task scheduling methodology for portable RC platforms .Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 3203 ,669-678

Handa M.;Vemuri R. (12-01-2004. ) An integrated online scheduling and placement methodology .Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 3203 ,444-453

Das A.;Vemuri R. (11-28-2007. ) An automated passive analog circuit synthesis framework using genetic algorithms.Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, , 145-150

Basu S.;Vemuri R. (11-28-2007. ) Process variation and NBTI tolerant standard cells to improve parametric yield and lifetime of ICs.Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, , 291-296

Sethuraman B.;Vemuri R. (12-17-2007. ) Multicasting based topology generation and core mapping for a power efficient networks-on-chip.Proceedings of the International Symposium on Low Power Electronics and Design, , 399-402

Ganesan S.;Vemuri R. (01-01-2001. ) Analog-digital partitioning for field-programmable mixed signal systems.Proceedings - 2001 Conference on Advanced Research in VLSI, ARVLSI 2001, , 172-185

Jia X.;Vemuri R. (12-01-2006. ) Studying a GALS FPGA architecture using a parameterized automatic design flow.IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, , 688-693

Handa M.;Vemuri R. (09-20-2004. ) An efficient algorithm for finding empty space for online FPGA placement.Proceedings - Design Automation Conference, , 960-965

Agarwal A.;Sampath H.;Yelamanchili V.;Vemuri R. (09-20-2004. ) Fast and accurate parasitic capacitance models for layout-aware synthesis of analog circuits .Proceedings - Design Automation Conference, , 145-150

Sethuraman B.;Vemuri R. (12-01-2006. ) Multi2 router: A novel multi LOCAL port router architecture with broadcast fa.Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL, , 795-798

Kommineni B.;Basu S.;Vemuri R. (12-01-2007. ) A spline based regression technique on interval valued noisy data.Proceedings - 6th International Conference on Machine Learning and Applications, ICMLA 2007, , 241-247

Das A.;Vemuri R. (07-22-2008. ) A self-learning optimization technique for topology design of computer networks.Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 4974 LNCS ,38-51

Basu S.;Kommineni B.;Vemuri R. (07-25-2008. ) Mismatch aware analog performance macromodeling using spline center and range regression on adaptive.Proceedings of the IEEE International Frequency Control Symposium and Exposition, , 287-293

Pradhan A.;Vemuri R. (12-01-2007. ) Regression based circuit matrix models for accurate performance estimation of analog circuits.2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC, , 48-53

Pradhan A.;Vemuri R. (07-25-2008. ) On the use of hash tables for efficient analog circuit synthesis.Proceedings of the IEEE International Frequency Control Symposium and Exposition, , 647-652

Sundaresan V.;Rammohan S.;Vemuri R. (12-01-2007. ) Power invariant secure IC design methodology using reduced complementary dynamic and differential lo.2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC, , 1-6

Rammohan S.;Sundaresan V.;Vemuri R. (07-25-2008. ) Reduced complementary dynamic and differential logic: A CMOS logic style for DPA-resistant secure IC.Proceedings of the IEEE International Frequency Control Symposium and Exposition, , 699-705

Sethuraman B.;Vemuri R. (12-01-2007. ) A force-directed approach for fast generation of efficient multi-port NoC architectures.Proceedings of the IEEE International Conference on VLSI Design, , 419-424

Yang H.;Vemuri R. (12-01-2007. ) Efficient symbolic sensitivity based parasitic-inclusive optimization in layout aware analog circuit.Proceedings of the IEEE International Conference on VLSI Design, , 201-206

Pradhan A.;Vemuri R. (08-25-2008. ) Fast analog circuit synthesis using sensitivity based near neighbor searches.Proceedings -Design, Automation and Test in Europe, DATE, , 523-526

Basu S.;Kommineni B.;Vemuri R. (08-26-2008. ) Variation aware spline center and range modeling for analog circuit performance.Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008, , 162-167

Das A.;Vemuri R. (09-17-2008. ) Topology synthesis of analog circuits based on adaptively generated building blocks.Proceedings - Design Automation Conference, , 44-49

Das A.;Vemuri R. (09-19-2008. ) ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework.Proceedings - IEEE International Symposium on Circuits and Systems, , 2542-2545

Sethuraman B.;Vemuri R. (12-01-2007. ) Power variations of multi-port routers in an application-specific NoC design: A case study.2007 IEEE International Conference on Computer Design, ICCD 2007, , 595-600

Pradhan A.;Vemuri R. (12-01-2008. ) A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection.Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, , 159-162

Xu H.;Vemuri R.;Jone W. (12-17-2008. ) Dynamic virtual ground voltage estimation for power gating.Proceedings of the International Symposium on Low Power Electronics and Design, , 27-32

Xu H.;Jone W.;Vemuri R. (12-26-2008. ) Accurate energy Breakeven time estimation for run-time power gating.IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, , 161-168

Xu H.;Vemuri R.;Jone W. (12-01-2008. ) Run-time active leakage reduction by power gating and reverse body biasing: An energy view.26th IEEE International Conference on Computer Design 2008, ICCD, , 618-625

Basu S.;Kommineni B.;Vemuri R. (03-30-2009. ) Variation-aware macromodeling and synthesis of analog circuits using spline center and range method .Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems, , 433-438

Das A.;Vemuri R. (03-30-2009. ) Fuzzy logic based guidance to graph grammar framework for automated analog circuit design.Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems, , 445-448

Pradhan A.;Vemuri R. (03-30-2009. ) Efficient synthesis of a uniformly spread layout aware pareto surface for analog circuits.Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems, , 131-136

Pradhan A.;Vemuri R. (04-22-2009. ) Accurate performance estimation using circuit matrix models in analog circuit synthesis.IFIP International Federation for Information Processing, , 291 ,131-150

Vemuri R.;Borowczak M.;Avakian A. (12-01-2008. ) Safety-centric design of distributed embedded avionics.National Aerospace and Electronics Conference, Proceedings of the IEEE, , 293-299

Sundaresan V.;Rammohan S.;Vemuri R. (12-01-2008. ) Defense against side-channel power analysis attacks on microelectronic systems.National Aerospace and Electronics Conference, Proceedings of the IEEE, , 144-150

Badaoui R.;Vemuri R. (12-01-2005. ) Analog VLSI circuit-level synthesis using multi-placement structures.Proceedings - IEEE International Symposium on Circuits and Systems, , 5978-5981

Hao X.;Vemuri R.;Jone W. (10-22-2009. ) Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic .Proceedings -Design, Automation and Test in Europe, DATE, , 594-597

Das A.;Vemuri R. (10-22-2009. ) A graph grammar based approach to automated multi-objective analog circuit design .Proceedings -Design, Automation and Test in Europe, DATE, , 700-705

Subramanian B.;Sethuraman ;Vemuri R. (11-06-2009. ) A methodology for application-specific noc architecture generation in a dynamic task structure envir.Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, , 149-152

Xu H.;Vemuri R.;Jone W.B. (12-01-2009. ) Temporal and spatial idleness exploitation for optimal-grained leakage control .IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, , 468-473

Xu H.;Jone W.;Vemuri R. (03-31-2010. ) Novel Vth hopping techniques for aggressive runtime leakage control.Proceedings of the IEEE International Conference on VLSI Design, , 51-56

Fernandes R.;Vemuri R. (12-01-2009. ) Accurate estimation of vector dependent leakage power in the presence of process variations.Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, , 451-458

Ouaiss I.;Vemuri R. (12-01-2000. ) Efficient resource arbitration in reconfigurable computing environments.Proceedings -Design, Automation and Test in Europe, DATE, , 560-566

Avakian A.;Nafziger J.;Panda A.;Vemuri R. (07-02-2010. ) A reconfigurable architecture for multicore systems.Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010, ,

Ouaiss I.;Vemuri R. (12-01-2001. ) Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers.Proceedings -Design, Automation and Test in Europe, DATE, , 650-657

Xu H.;Jone W.;Vemuri R. (12-01-2010. ) Stretching the limit of microarchitectural level leakage control with adaptive light-weight Vth hopp.IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, , 632-636

Xu H.;Vemuri R.;Jone W. (12-01-2010. ) Current shaping and multi-thread activation for fast and reliable power mode transition in multicore.IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, , 637-641

Xu H.;Vemuri R.;Jone W. (02-01-2011. ) Dynamic characteristics of power gating during mode transition.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 19 (2 ) ,237-249

Xu H.;Jone W.B.;Vemuri R. (10-01-2010. ) Tuning Vth hopping for aggressive runtime leakage control.Journal of Low Power Electronics, , 6 (3 ) ,447-456

Xu H.;Jone W.B.;Vemuri R. (07-01-2011. ) Aggressive runtime leakage control through adaptive light-weight V th hopping.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 19 (7 ) ,1319-1323

Nafziger J.;Avakian A.;Vemuri R. (12-01-2010. ) A prediction-based, data Migration Algorithm for hybrid Architecture NoC systems.Proceedings - IEEE International SOC Conference, SOCC 2010, , 435-440

Panda A.;Avakian A.;Vemuri R. (12-28-2011. ) Configurable workload generators for multicore architectures.International System on Chip Conference, , 179-184

Avakian A.;Agrawal N.;Vemuri R. (04-11-2012. ) Reconfigurable multicore architecture for dynamic processor reallocation.Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 7199 LNCS ,329-334

Yang H.;Ranjan M.;Verhaegen W.;Ding M.;Vemuri R.;Gielen G. (12-01-2005. ) Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams .Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, , 1 ,230-235

Ramakrishnan L.;Chakkaravarthy M.;Manchanda A.;Borowczak M.;Vemuri R. (07-27-2012. ) SDMLp: On the use of complementary pass transistor Logic for design of DPA resistant circuits.Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2012, , 31-36

Pattabiraman A.;Avakian A.;Vemuri R. (10-18-2012. ) A heterogeneous cache distribution with reconfigurable interconnect.Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012, , 271-276

Borowczak M.;Vemuri R. (06-12-2013. ) S*FSM: A paradigm shift for attack resistant fsm designs and encodings.Proceedings of the 2012 ASE International Conference on BioMedical Computing, BioMedCom 2012, , 96-100

Borowczak M.;Vemuri R. (12-01-2013. ) Secure controllers: Requirements of S*FSM.Midwest Symposium on Circuits and Systems, , 553-557

Teica E.;Radhakrishnan R.;Vemuri R. (12-01-2001. ) On the verification of synthesized designs using automatically generated transformational witnesses.Proceedings -Design, Automation and Test in Europe, DATE, , 798

Chawla P.;Walrath J.;Simone K.;Miles K.;Bellando J.;Hirsch H.;Vemuri R.;Sandstrom J.;Rubeiz M. (12-01-2001. ) Rapidly porting commercial electronic designs to radiationhardened domain .AIAA Space 2001 Conference and Exposition, ,

Balasubramanian V.;Xu H.;Vemuri R. (01-01-2013. ) Design automation flow for voltage adaptive optimum granularity LITHE for sequential circuits.International System on Chip Conference, , 355-360

Pan Y.;Li J.;Vemuri R. (01-01-2001. ) Continuous wavelet transform on reconfigurable meshes.Proceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001, , 1158-1163

Borowczak M.;Vemuri R. (01-01-2014. ) Enabling side channel secure FSMs in the presence of low power requirements.Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, , 232-235

Nair R.;Vemuri R. (01-01-2014. ) MITH-Dyn: A multi Vth dynamic logic design style using mixed mode FinFETs.International System on Chip Conference, , 140-145

Radhakrishnan R.;Teica E.;Vemuri R. (01-01-2001. ) Verification of basic block schedules using RTL transformations .Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 2144 ,173-178

Huang R.;Handa M.;Vemuri R. (01-01-2004. ) Analysis of a hybrid interconnect architecture for dynamically reconfigurable FPGAs .Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 3203 ,900-905

Jia X.;Rajagopalan J.;Vemuri R. (01-01-2004. ) A dynamically reconfigurable asynchronous FPGA architecture .Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 3203 ,836-841

Kasat A.;Ouaiss I.;Vemuri R. (01-01-2001. ) Memory synthesis for FPGA-based reconfigurable computers .Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 2147 ,70-80

Handa M.;Vemuri R. (01-01-2005. ) Hardware assisted two dimensional ultra fast online placement .International Journal of Embedded Systems, , 1 (3-4 ) ,291-299

Dasasathyan S.;Radhakrishnan R.;Vemuri R. (01-01-2002. ) Framework for synthesis of virtual pipelines.Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002, , 326-331

Yi H.;Tang S.;Vemuri R. (07-01-2016. ) Fast inversions in small finite fields by using binary trees.Computer Journal, , 59 (7 ) ,1102-1112

Komari P.;Vemuri R. (11-22-2016. ) A novel simulation based approach for trace signal selection in silicon debug.Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016, , 193-200

Liu X.;Vemuri R. (11-22-2017. ) Effective signal restoration in post-silicon validation.Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017, , 169-176

Liu X.;Vemuri R. (03-27-2018. ) Combined Inference and Satisfiability Based Methods for Complete Signal Restoration in Post-Silicon .Proceedings of the IEEE International Conference on VLSI Design, , 2018-January ,416-421

Lokare R.;Vemuri R. (03-26-2018. ) Progressive and secure performance unlocking for digital integrated circuits.2018 IEEE International Conference on Consumer Electronics, ICCE 2018, , 2018-January ,1-6

Nayak A.;Vemuri R. (03-26-2018. ) A secure tunable-precision architecture for image processing applications.2018 IEEE International Conference on Consumer Electronics, ICCE 2018, , 2018-January ,1-5

Chen S.;Vemuri R. (05-30-2018. ) Improving the security of split manufacturing using a novel BEOL signal selection method.Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, , 135-140

Agrawal R.;Vemuri R. (06-12-2018. ) On state encoding against power analysis attacks for finite state controllers.Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018, , 181-186

Liu X.;Vemuri R. (08-07-2018. ) Fast heuristics for near-optimal signal restoration in post-silicon validation.Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, , 2018-July ,34-39

Dharmadhikari P.;Raju A.;Vemuri R. (08-07-2018. ) Detection of sequential trojans in embedded system designs without scan chains.Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, , 2018-July ,678-683

Chen S.;Vemuri R. (01-16-2019. ) Reverse Engineering of Split Manufactured Sequential Circuits Using Satisfiability Checking.Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018, , 530-536

Chen S.;Vemuri R. (02-19-2019. ) On the Effectiveness of the Satisfiability Attack on Split Manufactured Circuits.IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, , 2018-October ,83-88

Liu X.;Vemuri R. (04-23-2019. ) Assertion Coverage Aware Trace Signal Selection in Post-Silicon Validation.Proceedings - International Symposium on Quality Electronic Design, ISQED, , 2019-March ,271-277

Kasarabada Y.;Chen S.;Vemuri R. (04-23-2019. ) On SAT-Based Attacks on Encrypted Sequential Logic Circuits.Proceedings - International Symposium on Quality Electronic Design, ISQED, , 2019-March ,204-211

Agrawal R.;Borowczak M.;Vemuri R. (05-09-2019. ) A state encoding methodology for side-channel security vs. Power trade-off exploration.Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019, , 70-75

Borowczak M.;Vemuri R. (07-01-2019. ) Mitigating information leakage during critical communication using S?FSM.IET Computers and Digital Techniques, , 13 (4 ) ,292-301

Chen S.;Vemuri R. (05-01-2019. ) Exploiting proximity information in a satisfiability based attack against split manufactured circuit.Proceedings of the 2019 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019, , 171-180

Kaul M.;Vemuri R. (12-01-1999. ) Temporal partitioning combined with design space exploration for latency minimization of run-time re.Proceedings -Design, Automation and Test in Europe, DATE, , 202-209

Roy J.;Kumar N.;Dutta R.;Vemuri R. (01-01-1992. ) DSS: A Disiributed High-Level Synthesis System.IEEE Design and Test of Computers, , 9 (2 ) ,18-32

Ganesan S.;Vemuri R. (12-01-2000. ) Technology mapping and retargeting for field-programmable analog arrays.Proceedings -Design, Automation and Test in Europe, DATE, , 58-64

Vemuri R.;Kumar N.;Vutukuru R.;Rao P.;Sinha P.;Ren N.;Mamtora P.;Mandayam R.;Vemuri R.;Roy J. (01-01-1993. ) An Integrated Multicomponent Synthesis Environment for MCMs.Computer, , 26 (4 ) ,62-74

Koutsougeras C.;Papachristou C.A.;Vemuri R.R. (12-01-1986. ) DATA FLOW GRAPH PARTITIONING TO REDUCE COMMUNICATION COST. MICRO: Annual Microprogramming Workshop, , 82-91

Vemuri R. (12-01-1989. ) On the effectiveness of a system of RT-level transformations for design-space exploration .Midwest Symposium on Circuits and Systems, , 1078-1084

Vemuri R. (12-01-1990. ) How to prove the completeness of a set of register level design transformations .27th ACM/IEEE Design Automation Conference. Proceedings 1990, , 207-212

Sridhar A.;Vemuri R. (12-01-1990. ) Automatic precondition verification for high-level design transformations .Proceedings - IEEE International Symposium on Circuits and Systems, , 4 ,2654-2657

Kumar N.;Vemuri R. (12-01-1992. ) Finite state machine verification on MIMD machines .European Design Automation Conference, , 514-520

Dutta R.;Roy J.;Vemuri R. (12-01-1992. ) Distributed design-space exploration for high-level synthesis systems .Proceedings - Design Automation Conference, , 644-650

Mandayam R.;Vemuri R. (01-01-1993. ) Performance specification using attributed grammars .Proceedings - Design Automation Conference, , 661-667

Vemuri R.;Mamtora P.;Sinha P.;Kumar N.;Roy J.;Vetukuru R. (01-01-1993. ) Experience in functional validation of a high level synthesis system .Proceedings - Design Automation Conference, , 194-201

Mandayam R.;Vemuri R. (12-01-1993. ) Performance specification and measurement .IFIP Transactions A: Computer Science and Technology, , (A-32 ) ,281-298

Vemuri R. (01-01-1994. ) MCM layer assignment using genetic search.Electronics Letters, , 30 (20 ) ,1635-1637

Vemuri R. (08-04-1994. ) Genetic algorithms for MCM partitioning.Electronics Letters, , 30 (16 ) ,1270-1271

Kumar N.;Katkoori S.;Rader L.;Vemuri R. (01-01-1995. ) Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems.IEEE Design and Test of Computers, , 12 (3 ) ,70-84

Katkoori S.;Kumar N.;Vemuri R. (12-01-1995. ) High level profiling based low power synthesis technique .Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, , 446-452

Bradley W.;Vemuri R. (12-01-1995. ) Performance verification using PDL and constraint satisfaction .Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, , 531-538

Katkoori S.;Kumar N.;Rader L.;Vemuri R. (12-01-1995. ) Profile driven approach for low power synthesis .Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, , 759-766

Katkoori S.;Roy J.;Vemuri R. (01-01-1996. ) Hierarchical register optimization algorithm for behavioral synthesis .Proceedings of the IEEE International Conference on VLSI Design, , 126-132

Katkoori S.;Vemuri R. (01-01-1996. ) Simulation based architectural power estimation for PLA-based controllers .International Symposium on Low Power Electronics and Design, Digest of Technical Papers, , 121-124

Narasimhan N.;Roy J.;Vemuri R. (01-01-1996. ) Synchronous controller models for synthesis from communicating VHDL processes .Proceedings of the IEEE International Conference on VLSI Design, , 198-204

Kumar N.;Srinivasan V.;Vemuri R. (01-01-1996. ) Hierarchical behavioral partitioning for multicomponent synthesis .European Design Automation Conference - Proceedings, , 212-217

Narasimhan N.;Srinivasan V.;Vootukuru M.;Walrath J.;Govindarajan S.;Vemuri R. (01-01-1996. ) Rapid prototyping of reconfigurable coprocessors .International Conference on Application-Specific Systems, Architectures and Processors, Proceedings, , 303-312

Walrath J.;Chatha K.;Vemuri R.;Narasimhan N.;Srinivasan V. (01-01-1996. ) Performance modeling and tradeoff analysis during rapid prototyping .International Conference on Application-Specific Systems, Architectures and Processors, Proceedings, , 313-322

Vemuri R.;Mandayam R.;Meduri V. (04-01-1996. ) Performance modeling using PDL.Computer, , 29 (4 ) ,44-53

Katkoori S.;Vemuri R. (12-01-1996. ) Simulation based architectural power estimation for PLA-based controllers .IEEE Symposium on Low Power Electronics, , 121-124

Walrath J.;Vemuri R.;Bradley W. (01-01-1997. ) Performance verification using partial evaluation and interval analysis .Proceedings of European Design and Test Conference, , 622

Govindarajan S.;Vemuri R. (01-01-1997. ) Cone-based clustering heuristic for list-scheduling algorithms .Proceedings of European Design and Test Conference, , 456-462

Natesan V.;Gupta A.;Katkoori S.;Bhatia D.;Vemuri R. (01-01-1997. ) Constructive method for data path area estimation during high-level VLSI synthesis .Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, , 509-515

Walrath J.;Vemuri R. (01-01-1997. ) Symbolic evaluation of performance models for tradeoff visualization .Proceedings - Design Automation Conference, , 359-364

Vootukuru M.;Vemuri R.;Kumar N. (01-01-1997. ) Resource constrained RTL partitioning for synthesis of multi-FPGA designs .Proceedings of the IEEE International Conference on VLSI Design, , 140-144

Govindarajan S.;Vemuri R. (12-01-1997. ) Dynamic bounding of successor force computations in the Force Directed List Scheduling Algorithm .Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, , 752-757

Katkoori S.;Vemuri R. (01-01-1998. ) Architectural power estimation based on behavior level profiling.VLSI Design, , 7 (3 ) ,255-270

Chatha K.;Vemuri R. (01-01-1998. ) Performance evaluation tool for rapid prototyping of hardware-software codesigns .Proceedings of the International Workshop on Rapid System Prototyping, , 218-224

Srinivasan V.;Vemuri R. (01-01-1998. ) Retiming based relaxation heuristic for resource-constrained loop pipelining .Proceedings of the IEEE International Conference on VLSI Design, , 435-441

Chatha K.;Vemuri R. (01-01-1998. ) RECOD: A retiming heuristic to optimize resource and memory utilization in HW/SW codesigns .Hardware/Software Codesign - Proceedings of the International Workshop, , 139-143

Dhanwada N.;Vemuri R. (01-01-1998. ) Constraint allocation in analog system synthesis .Proceedings of the IEEE International Conference on VLSI Design, , 253-258

Narasimhan N.;Teica E.;Radhakrishnan R.;Govindarajan S.;Vemuri R. (12-01-1998. ) Theorem proving guided development of formal assertions in a resource-constrained scheduler for high .Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, , 392-399

Paruthi V.;Mansouri N.;Vemuri R. (12-01-1998. ) Automatic data path abstraction for verification of large scale designs .Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, , 192-194

Chawla P.;Alexander P.;Vemuri R. (12-01-1998. ) Search and retrieval tool to enable system design through intellectual property reuse .National Aerospace and Electronics Conference, Proceedings of the IEEE, , 620-626

Chatha K.;Vemuri R. (01-01-1999. ) Iterative algorithm for partitioning and scheduling of area constrained HW-SW systems .Proceedings of the International Workshop on Rapid System Prototyping, , 134-139

Dhanwada N.;Nunez-Aldana A.;Vemuri R. (01-01-1999. ) Genetic approach to simultaneous parameter space exploration and constraint transformation in analog .Proceedings - IEEE International Symposium on Circuits and Systems, , 6 ,

Doboli A.;Nunez-Aldana A.;Dhanwada N.;Ganesan S.;Vemuri R. (01-01-1999. ) Behavioral synthesis of analog systems using two-layered design space exploration .Proceedings - Design Automation Conference, , 951-957

Kaul M.;Vemuri R.;Govindarajan S.;Ouaiss I. (01-01-1999. ) Automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of .Proceedings - Design Automation Conference, , 616-622

Ganesan S.;Vemuri R. (01-01-1999. ) FAAR: A router for field-programmable analog arrays .Proceedings of the IEEE International Conference on VLSI Design, , 556-563

Dhanwada N.R.;Nunez-Aldana A.;Vemuri R. (01-01-1999. ) Component characterization and constraint transformation based on directed intervals for analog synt .Proceedings of the IEEE International Conference on VLSI Design, , 589-596

Ghosh A.;Vemuri R. (12-01-1999. ) Formal verification of synthesized analog designs .Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, , 40-45

Ganesan S.;Vemuri R. (12-01-1999. ) Methodology for rapid prototyping of analog systems .Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, , 482-488

Katkoori S.;Vemuri R. (12-01-1999. ) Accurate resource estimation algorithms for behavioral synthesis .Proceedings of the IEEE Great Lakes Symposium on VLSI, , 338-339

Pandey A.;Vemuri R. (12-01-1999. ) Combined temporal partitioning and scheduling for reconfigurable architectures .Proceedings of SPIE - The International Society for Optical Engineering, , 3844 ,93-103

Ganesan S.;Vemuri R. (12-01-1999. ) FPGA/FPAA-based rapid prototyping environment for mixed signal systems .Proceedings of SPIE - The International Society for Optical Engineering, , 3844 ,49-60

Ghosh A.;Lodha S.;Vemuri R. (12-01-1999. ) Hierarchical scheduling in high level synthesis using resource sharing across nested loops .Proceedings of the IEEE Great Lakes Symposium on VLSI, , 140-143

Srinivasan V.;Vemuri R. (12-01-1999. ) Task-level partitioning and RTL design space exploration for multi-FPGA architectures .IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings, , 272-273

Mansouri N.;Vemuri R. (01-01-2000. ) Automated correctness condition generation for formal verification of synthesized RTL designs.Formal Methods in System Design, , 16 (1 ) ,59-91

Doboli A.;Dhanwada N.;Vemuri R. (01-01-2000. ) Heuristic technique for system-level architecture generation from signal-flow graph representations .Proceedings - IEEE International Symposium on Circuits and Systems, , 3 ,

Katkoori S.;Vemuri R. (01-01-2000. ) Scheduling for low power under resource and latency constraints .Proceedings - IEEE International Symposium on Circuits and Systems, , 2 ,

Govindarajan S.;Srinivasan V.;Lakshmikanthan P.;Vemuri R. (01-01-2000. ) Technique for dynamic high-level exploration during behavioral-partitioning for multi-device archite .Proceedings of the IEEE International Conference on VLSI Design, , 212-219

Kaul M.;Vemuri R. (01-01-2000. ) Design-space exploration for block-processing based temporal partitioning of run-time reconfigurable .Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, , 24 (2 ) ,181-209

Ghosh A.;Vemuri R. (01-01-2000. ) Formal verification of synthesized mixed signal designs using*BMDs .Proceedings of the IEEE International Conference on VLSI Design, , 84-90

Vemuri R.;Harr R. (04-01-2000. ) Configurable computing: Technology and applications.Computer, , 33 (4 ) ,39-40

Chatha K.S.;Vemuri R. (08-01-2000. ) Iterative algorithm for hardware-software partitioning, hardware design space exploration and schedu .Design Automation for Embedded Systems, , 5 (3 ) ,281-293

Vemuri R.;Walrath J. (12-01-1998. ) Abstract models of reconfigurable architectures for synthesis and compilation.Proceedings of SPIE - The International Society for Optical Engineering, , 3526 ,162-175

Mansouri N.;Vemuri R. (01-01-1998. ) A methodology for automated verification of synthesized RTL designs and its integration with a high- .Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 1522 ,102-204

Mansouri N.;Vemuri R. (12-01-1999. ) Accounting for various register allocation schemes during post-synthesis verification of RTL designs.Proceedings -Design, Automation and Test in Europe, DATE, , 223-230

Kaul M.;Vemuri R. (12-01-1998. ) Optimal temporal partitioning and synthesis for reconfigurable architectures.Proceedings -Design, Automation and Test in Europe, DATE, , 389-396

Nunez-Aldana A.;Vemuri R. (12-01-1999. ) An analog performance estimator for improving the effectiveness of CMOS analog systems circuit synth.Proceedings -Design, Automation and Test in Europe, DATE, , 406-411

Narasimhan N.;Vemuri R. (01-01-1998. ) On the effectiveness of theorem proving guided discovery of formal assertions for a register allocat .Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 1479 ,367-386

Lakshmikanthan P.;Govindarajan S.;Srinivasan V.;Vemuri R. (12-01-2000. ) Behavioral partitioning with synthesis for Multi-FPGA architectures under interconnect, area, and la .Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 1800 LNCS ,924-931

Doboli A.;Vemuri R. (12-01-1999. ) A VHDL-AMS compiler and architecture generator for behavioral synthesis of analog systems.Proceedings -Design, Automation and Test in Europe, DATE, , 338-345

Dhanwada N.;Nunez-Aldana A.;Vemuri R. (12-01-1999. ) Hierarchical constraint transformation using directed interval search for analog system synthesis.Proceedings -Design, Automation and Test in Europe, DATE, , 328-335

Govindarajan S.;Ouaiss I.;Kaul M.;Srinivasan V.;Vemuri R. (01-01-1998. ) An effective design system for dynamically reconfigurable architectures.Proceedings - IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998, , 1998-April ,1-2

Vemuri R.;Kalyanaraman R. (01-01-1995. ) Generation of Design Verification Tests from Behavioral VHDL Programs Using Path Enumeration and Con.IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 3 (2 ) ,201-214

Srinivasan V.;Radhakrishnan S.;Vemuri R. (12-01-1998. ) Hardware software partitioning with integrated hardware design space exploration.Proceedings -Design, Automation and Test in Europe, DATE, , 28-35

Vemuri R. (01-01-1991. ) Genetic synthesis: Performance-driven logic synthesis using genetic evolution.Proceedings - 1st Great Lakes Symposium on VLSI, GLSV 1991, , 312-317

Vemuri R. (01-01-1990. ) On the notion of the normal form register-level structures and its applications in design-space expl.Proceedings of the European Design Automation Conference, EDAC 1990, , 46-51

Ouaiss I.;Govindarajan S.;Srinivasan V.;Kaul M.;Vemuri R. (01-01-1998. ) An integrated partitioning and synthesis system for dynamically reconfigurable multi-FPGA architectu .Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 1388 ,31-36

Walrath J.;Vemuri R. (01-01-1998. ) A performance modeling and analysis environment for reconfigurable computers .Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 1388 ,19-24

Govindarajan S.;Vemuri R. (01-01-2000. ) Tightly integrated design space exploration with spatial and temporal partitioning in SPARCS .Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 1896 ,7-18

Chatha K.S.;Vemuri R. (12-02-1998. ) A tool for partitioning and pipelined scheduling of hardware-software systems .Proceedings of the International Symposium on System Synthesis, , Part F129250 ,145-151

Chatha K.S.;Vemuri R. (01-01-1999. ) Hardware-software codesign for dynamically reconfigurable architectures .Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 1673 ,175-185

Srinivasan V.;Radhakrishnan S.;Vemuri R.;Walrath J. (01-01-1999. ) Interconnect synthesis for reconfigurable multi-FPGA architectures.Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 1586 ,588-596

Kaul M.;Vemuri R. (01-01-1999. ) Integrated block-processing and design-space exploration in temporal partitioning for RTR architectu.Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 1586 ,606-615

Narasimhan N.;Vemuri R. (01-01-1996. ) Specification of control flow properties for verification of synthesized VHDL designs.Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 1166 ,327-345

Vemuri R.;Hoffa R.;Vemuri R. (01-01-1992. ) An application of genetic algorithms to solve the layer assignment problem in multi chip modules.Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics, , 1992-January ,1520-1525

Vemuri R. (08-04-1994. ) Genetic algorithm for MCM partitioning.Electronics Letters, , 30 (16 ) ,1270-1272

Vemuri R.;Sridhar A. (01-01-1992. ) Temporal precondition verification of design transformations.Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), , 575 LNCS ,125-135

Walrath J.;Vemuri R.;Bradley W. (03-17-1997. ) Performance verification using partial evaluation and interval analysis .Proceedings of the 1997 European Conference on Design and Test, EDTC 1997, , 622

Govindarajan S.;Vemuri R. (03-17-1997. ) Cone-based clustering heuristic for list-scheduling algorithms .Proceedings of the 1997 European Conference on Design and Test, EDTC 1997, , 456-462

Núñez-Aldana A.;Vemuri R. (01-01-1999. ) Two level performance estimator for high level synthesis of analog integrated circuits with feedback.Proceedings of the 3rd International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, , 167-170

Other Information

https://scholar.google.com/citations?user=Yq8TtKcAAAAJ&hl=en&oi=ao,